The present invention relates generally to electronic devices and more particularly to a method and system for decoding 8-bit/10-bit data in switching circuits using limited-width decoding devices.
Many systems, including most Fibre Channel systems, use an 8B/10B encoding scheme. In this scheme, 8-bit data is encoded into 10-bit data before it is transmitted from one device to another. Encoded 10-bit data that is received by a device is decoded to produce the original 8-bit data, which can then be processed normally within the device. 8B/10B encoding is described in U.S. Pat. No. 4,483,739 to IBM issued in 1994 which is incorporated by reference herein.
One of the motivations for using 8B/10B encoding is that it allows certain characteristics of the encoded data to be controlled. For example, the total number of ones and zeros can be made essentially equal, and the number of consecutive ones or zeros can be limited. These characteristics are desirable because the quality of the data signal may degraded as a result of shifts induced by a shifting DC-component. Another motivation behind the use of 8B/10B encoding is the ability to use special code words which would be impossible if no encoding was performed.
Every ten bit code group must fit into one of the following three possibilities: five ones and five zeros; four ones and six zeros; or six ones and four zeros. This requirement helps limit the number of consecutive ones and zeros between any two code groups (10-bit data words) and balances the numbers of ones and zeros.
While the use of 8B/10B encoding maintains the DC component of the data signal at a nearly stationary level, additional DC balancing is achieved through the use of a disparity (or running disparity) calculation. The concept of disparity is used to keep the number of ones in a data signal equal to the number of zeros in that data signal. If the number of ones and the number of zeros are equal, the DC level should remain balanced halfway between the xe2x80x98onexe2x80x99 voltage level and the xe2x80x98zeroxe2x80x99 voltage level. Disparity can be either positive or negative. Normally, the disparity is positive if more ones have been transmitted than zeros and negative if more zeros have been transmitted than ones (since the last reset event.)
Certain hardware devices such as programmable logic devices (PLDs) or programmable gate arrays (PGAs), contain logic blocks. Each logic block has a limited number of inputs and outputs. In one instance, the logic blocks may be able to accommodate 8-bit data. In this case, the decoding of 10-bit data obviously cannot be performed by a single logic block because the data is too wide for the logic block. While additional logic blocks can be used, the 10-bit data cannot simply be broken into two smaller blocks that could be independently decoded, then combined to form a decoded 8-bit data word.
The logic blocks would instead have to be cascaded (placed in series with one another) together to create a decoder which is sufficiently large to handle the entire 10-bit data word. Cascading the logic blocks, however, greatly reduces operating speed. For an 8-bit/10-bit decoder, many additional layers of logic are required. Each of these logic layers decreases the operating speed of the decoder.
It should be noted that 8B/10B decoding actually requires an input width of 11 bits (10 data bits plus a current disparity bit.) The decoding process produces an output of 9 bits (8 data bits plus a xe2x80x9cKxe2x80x9d character indicator.) All 11 bits must be considered when generating the 9 bits of output data.
In designing a device that performs 8B/10B decoding, conventional logic design tools may be used. These tools implement conventional design rules which may lead to the type of cascaded designs described above. The resulting devices typically run so slowly that they do not comprise viable products. In addition to the decrease in speed caused by the cascading of logic blocks, the device designs produced by conventional tools may waste a considerable amount of logic. For example, while a first 8-bit logic block may be fully utilized, a second 8-bit logic block may be used to handle only the 2-3 bits of data that could not be accommodated by the first block. The remaining 5-6 bits are wasted. It is therefore necessary to consider alternative approaches for decoding the 8B/10B data.
There is a need, therefore, for a method and system for providing 8B/10B decoding using the fewer than 11 inputs and 9 outputs per block. There is a need for a method and system to reduce the total number of logic blocks required to implement a decoding between 8 and 10-bit data in a fibre channel switching circuit.
In accordance with the present invention, a method and system for decoding 8B/10B data with limited width decoders is provided. The disadvantages and problems associated with previously developed decoder methods and systems may be thereby substantially eliminated or reduced.
According to one aspect of the invention, there is provided a method for decoding an 8B/10B-encoded data word using a switching circuit comprising a set of logic devices having data widths that are less than the width of the encoded data word. In one embodiment, the method includes the steps of determining the presence of one of a plurality of predetermined data sequences within a first portion of a data word, translating the predetermined data sequences into representative signals having a smaller aggregate data width than the first portion of the data word, and providing the representative signals together with remaining portions of the data word to a logic block for decoding.
According to another aspect of the invention, there is provided a device for decoding 8B/10-encoded data, wherein the device uses logic blocks that have smaller data widths than the encoded data. In one embodiment, the device includes at least two pipeline stages. In the first pipeline stage, a portion of each encoded data word is pre-decoded to produce one or more flags having an aggregate data width which is less than the width of the pre-decoded portion of the data word. In the second pipeline stage, the remaining portion of the encoded data word is decoded using the one or more flags. The pre-decoded portion of the data word is also decoded in the second pipeline stage.
One advantage of the present invention is that it makes possible a practical 8-bit/10-bit decoder function that includes disparity and K character indicators that may be implemented in a device containing blocks having fewer than 11 inputs and 9 outputs per block.
The present invention can also reduce the speed penalty associated with cascaded layers of logic by taking particular groups of bits of the encoded data and pre-decoding them. The pre-decode function forms a pipeline stage that converts a set of bits from an encoded data word into fewer equivalent bits. Then, in a subsequent pipeline stage, the equivalent bits, combined with the remaining bits of the encoded data word, can be decoded to produce the decoded data word.